The present invention relates to a microprocessor; and, more particularly, to an apparatus for generating a breakpoint interrupt of computer program.
In the process of developing a computer software program, a program debugging is performed for analyzing the performance of the program and eliminating errors in the program. The debugging is considered to be important part in the development of a program and often requires more time than the composition of the program does.
A method for debugging a computer program is that events to be desired for observation are pre-determined and then when such events occurs in the trial execution of the program for debugging, the execution is stalled for inspection of the values stored in programmer visible registers and so on. For example, in order to inspect program and data stored in a memory at a specific case, an address to be used for the specific case is pre-set and then, when the generated address is matched with the pre-set address, a breakpoint is generated. When the breakpoint is generated, the program execution is stalled for the inspection of the program context.
There have been proposed various approaches for generating such breakpoint interrupts and one of them is to modify the program, which is inserting a software interrupt instructions at a specific address of the software program. However, though such a method can be easily implemented, it has a disadvantage in that a breakpoint can not be set for the address referring to data.
Another approach for generating a breakpoint interrupt is a hardware-implementation provided outside a microprocessor or a computer. Such hardware compares a generated address by computer with a pre-set address and, if any match is made, it sends a hardware interrupt signal to the microprocessor or the computer so as to stop the execution. However, such method needs much cost for implementation and additive space for printed circuit board of the hardware. In addition, for a high-speed processor, the breakpoint interrupt hardware can not in general accord with the processor in speed, whereby the breakpoint interrupt is not actually generated in time but later time. Also, when the processor has an address generation unit on the same chip, since the address to be seen from the outside of the processor is not a logical address of the program but a physical address for memory access, the breakpoint interrupt generation can not be made by this approach.
A still another approach is that an apparatus for generating breakpoint is provided within the processor, in which the apparatus includes a plurality of address registers for storing the pre-set addresses to be compared, a plurality of control registers for storing control information related to the breakpoint generation, and a comparator for comparing one of the pre-set addresses with a generated address by the processor.
When such a method is applied to RISC (Reduced Instruction Set Computer) processor, the length of instruction and data are always the same (e.g. always 4 bytes (=32 bits)) and the values to be compared are multiples of 4. Therefore, the implementation of comparator is easy. However, in a CISC (complex Instruction Set Computer) processor such as X86 series of Intel, the length of instruction and data are varying. Therefore, for implementation, a large quantity of hardware resource is needed. Here, if the breakpoint address and the range thereof are provided with constraints, the design of comparator becomes more or less easy. For example, in the case of 386 processor of Intel, the design of comparator can be easy by providing with the constraint in that any value can be compared if the range of the breakpoint address is xe2x80x9c1xe2x80x9d; only even addresses can be compared if xe2x80x9c2xe2x80x9d; and only the addresses of 4""s multiple can be allowed to be compared if xe2x80x9c4xe2x80x9d.
However, in an n-way superscalar processor such as a Pentium processor of Intel, since multiple reference addresses are generated during one cycle, each of breakpoint address registers should have n read ports and n comparators each for comparing a corresponding breakpoint address register. Thus, there is a problem that considerable amount of hardware resources are required.
Next, a conventional address match circuit in an apparatus for generating breakpoint is shown in FIG. 1, which is for the case that there is no constraint in the breakpoint address and the range of the breakpoint address. Especially, FIG. 1 is a schematic block diagram of an address match circuit in a conventional apparatus for generating breakpoint.
A start address Bstart of breakpoint is set from the breakpoint address register and then the breakpoint address is added with a range value R by the first adder 100 so that a stop address Bstop of the breakpoint address is produced. For example, if the value of the breakpoint address register is FFF in hexadecimal and the R is 4 bytes, then Bstart is FFF and Bstop is 1002. Also, for the address generated from an address generation unit, a start address Mstart for memory reference is determined and the Mstart is added with the operand size OS so that a stop address of memory reference is generated. For example, if the generated address from the address generation unit is 1000 in hexadecimal and OS is 2 bytes, then Mstart is 1000 in hexadecimal and Mstop is 1001 in hexadecimal.
Next, for generating a breakpoint interrupt, the following conditions 1 and 2 must be satisfied between Bstart, Bstop, Mstart, and Mstop.
[Condition 1]
Bstartxe2x89xa6Mstop
[Condition 2]
Mstartxe2x89xa6Bstop
For doing this, Bstart, Bstop, Mstart and Mstop are compared with one another by the first and the second comparators 140 and 160 and then the compared results are logic-ANDed in a AND gate 180 so as to produce a final match signal. For instance, if Bstart is FFF in hexadecimal, Bstop 1002 in hexadecimal, Mstart 1000 in hexadecimal and Mstop 1001 in hexadecimal, then the above condition is satisfied and thus a final address match signal is generated.
As described above, the conventional apparatus for generating breakpoint without any constraint between the breakpoint address and the range of the breakpoint address, requires much hardware resources such as adder, comparator and logic AND gate in order to confirm whether there is any match for breakpoint address. Thus, the time for generating match signal becomes critical.
The present invention is addressed to solve the above problem. The object of the present invention is to provide an apparatus for generating breakpoint in a superscalar microprocessor, which is capable of being implemented by small amount of hardware resources and thus the required chip area can be reduced.
An other object of the present invention is to provide an address match circuit, which can be used for generating a breakpoint interrupt in a superscalar microprocessor and implemented with small amount of hardware resources, thereby reducing the required chip-area therefor.
According to one preferred embodiment of the present invention in order to achieve the above object, there is provided a breakpoint interrupt generation apparatus in a n-way superscalar microprocessor comprising: an address control means for receiving a plurality of addresses and a plurality of request signals generated for memory access and for producing the received address one-by-one for one cycle; a breakpoint address storage for storing an intended address for breakpoint generation; a control information storage for storing control information required for breakpoint generation; an address match means for comparing the address from said breakpoint address storage and the address applied from the address control means so as to produce a match signal indicating whether the two addresses are identical; and an enable means for checking whether a breakpoint is generated every cycle based on the match signal from the address match means, the control information from the control information storage and a bus cycle information and for generating a breakpoint interrupt signal in response to a complete signal from the address control means.
In accordance with another embodiment of the present invention, there is provided a breakpoint interrupt generation apparatus in an n-way superscalar microprocessor comprising: an address control means for inputting n addresses in parallel and then producing one by one the inputted address every cycle and outputting a stall signal and a complete signal, said stall signal indicating that an input operation for the next n addresses should be installed until all of the inputted addresses being outputted, and said complete signal indicating when all of the inputted addresses are outputted; a breakpoint address memory for storing at least one breakpoint address; an address match means for comparing the output of the address control means with the breakpoint address, so as to produce an address match signal; and a logic means for generating a breakpoint interrupt based on the address match signal when the complete signal is generated.
The breakpoint interrupt generation apparatus further comprises a mode register indicating whether an operation mode of the breakpoint interrupt generation apparatus is xe2x80x9cdebugging modexe2x80x9d and said address control means is enabled when the mode register indicates the debugging mode.
In accordance with another aspect of the present invention, there is provided an address match circuit in a breakpoint interrupt generation apparatus of a superscalar microprocessor, for detecting whether an inputted address corresponds to a predetermined range of address requiring a breakpoint interrupt generation, comprising: a breakpoint address memory for storing a breakpoint address that is start address requiring a breakpoint interrupt generation; a range memory for storing the predetermined range of address; an operand size memory for storing a size value of an operand being performed; a subtractor for subtracting the inputted address from the breakpoint address; and a detecting means for detecting that the output of the subtractor is equal to or larger than an inverted value of the size value of the operand and that the output of the subtractor is equal to or less than the predetermined range of address.
When the output of the subtractor is M-bits and both of the operand size and the address range are represented by L-bits, said detecting means comprises: a first detector for detecting that all of the upper M-L bits of the output of the subtractor are xe2x80x9c0xe2x80x9d; a second detector for detecting that all of the upper M-L bits of the output of the subtractor are xe2x80x9c1xe2x80x9d; a first comparator for comparing so as to detect that the least L bits of the output of the subtractor is equal to or less than the address range; a second comparator for comparing so as to detect that the least L bits of the output of the subtractor is equal to or larger than an inverted value of the operand size; and a logic means for producing the address match signal based on the outputs of the first and the second detectors and the first and the second comparators.